ChampSim
cache.h
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1 /*
2  * Copyright 2023 The ChampSim Contributors
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifdef CHAMPSIM_MODULE
18 #define SET_ASIDE_CHAMPSIM_MODULE
19 #undef CHAMPSIM_MODULE
20 #endif
21 
22 #ifndef CACHE_H
23 #define CACHE_H
24 
25 #include <array>
26 #include <bitset>
27 #include <deque>
28 #include <memory>
29 #include <stdexcept>
30 #include <string>
31 #include <vector>
32 
33 #include "champsim.h"
34 #include "champsim_constants.h"
35 #include "channel.h"
36 #include "module_impl.h"
37 #include "operable.h"
38 #include <type_traits>
39 
40 struct cache_stats {
41  std::string name;
42  // prefetch stats
43  uint64_t pf_requested = 0;
44  uint64_t pf_issued = 0;
45  uint64_t pf_useful = 0;
46  uint64_t pf_useless = 0;
47  uint64_t pf_fill = 0;
48 
49  std::array<std::array<uint64_t, NUM_CPUS>, champsim::to_underlying(access_type::NUM_TYPES)> hits = {};
50  std::array<std::array<uint64_t, NUM_CPUS>, champsim::to_underlying(access_type::NUM_TYPES)> misses = {};
51 
52  double avg_miss_latency = 0;
53  uint64_t total_miss_latency = 0;
54 };
55 
56 class CACHE : public champsim::operable
57 {
58  enum [[deprecated(
59  "Prefetchers may not specify arbitrary fill levels. Use CACHE::prefetch_line(pf_addr, fill_this_level, prefetch_metadata) instead.")]] FILL_LEVEL{
60  FILL_L1 = 1, FILL_L2 = 2, FILL_LLC = 4, FILL_DRC = 8, FILL_DRAM = 16};
61 
65 
66  struct tag_lookup_type {
67  uint64_t address;
68  uint64_t v_address;
69  uint64_t data;
70  uint64_t ip;
71  uint64_t instr_id;
72 
73  uint32_t pf_metadata;
74  uint32_t cpu;
75 
78  bool skip_fill;
80  bool translate_issued = false;
81 
82  uint8_t asid[2] = {std::numeric_limits<uint8_t>::max(), std::numeric_limits<uint8_t>::max()};
83 
84  uint64_t event_cycle = std::numeric_limits<uint64_t>::max();
85 
86  std::vector<std::reference_wrapper<ooo_model_instr>> instr_depend_on_me{};
87  std::vector<std::deque<response_type>*> to_return{};
88 
89  explicit tag_lookup_type(request_type req) : tag_lookup_type(req, false, false) {}
90  tag_lookup_type(request_type req, bool local_pref, bool skip);
91  };
92 
93  struct mshr_type {
94  uint64_t address;
95  uint64_t v_address;
96  uint64_t data;
97  uint64_t ip;
98  uint64_t instr_id;
99 
100  uint32_t pf_metadata;
101  uint32_t cpu;
102 
105 
106  uint8_t asid[2] = {std::numeric_limits<uint8_t>::max(), std::numeric_limits<uint8_t>::max()};
107 
108  uint64_t event_cycle = std::numeric_limits<uint64_t>::max();
109  uint64_t cycle_enqueued;
110 
111  std::vector<std::reference_wrapper<ooo_model_instr>> instr_depend_on_me{};
112  std::vector<std::deque<response_type>*> to_return{};
113 
114  mshr_type(tag_lookup_type req, uint64_t cycle);
115  static mshr_type merge(mshr_type predecessor, mshr_type successor);
116  };
117 
118  bool try_hit(const tag_lookup_type& handle_pkt);
119  bool handle_fill(const mshr_type& fill_mshr);
120  bool handle_miss(const tag_lookup_type& handle_pkt);
121  bool handle_write(const tag_lookup_type& handle_pkt);
122  void finish_packet(const response_type& packet);
123  void finish_translation(const response_type& packet);
124 
125  void issue_translation();
126 
127  struct BLOCK {
128  bool valid = false;
129  bool prefetch = false;
130  bool dirty = false;
131 
132  uint64_t address = 0;
133  uint64_t v_address = 0;
134  uint64_t data = 0;
135 
136  uint32_t pf_metadata = 0;
137 
138  BLOCK() = default;
139  explicit BLOCK(mshr_type mshr);
140  };
141  using set_type = std::vector<BLOCK>;
142 
143  std::pair<set_type::iterator, set_type::iterator> get_set_span(uint64_t address);
144  std::pair<set_type::const_iterator, set_type::const_iterator> get_set_span(uint64_t address) const;
145  std::size_t get_set_index(uint64_t address) const;
146 
147  template <typename T>
148  bool should_activate_prefetcher(const T& pkt) const;
149 
150  template <bool>
151  auto initiate_tag_check(champsim::channel* ul = nullptr);
152 
153  std::deque<tag_lookup_type> internal_PQ{};
154  std::deque<tag_lookup_type> inflight_tag_check{};
155  std::deque<tag_lookup_type> translation_stash{};
156 
157 public:
158  std::vector<channel_type*> upper_levels;
161 
162  uint32_t cpu = 0;
163  const std::string NAME;
164  const uint32_t NUM_SET, NUM_WAY, MSHR_SIZE;
165  const std::size_t PQ_SIZE;
166  const uint64_t HIT_LATENCY, FILL_LATENCY;
167  const unsigned OFFSET_BITS;
169  const long int MAX_TAG, MAX_FILL;
170  const bool prefetch_as_load;
171  const bool match_offset_bits;
172  const bool virtual_prefetch;
173  bool ever_seen_data = false;
175 
177 
179 
180  std::deque<mshr_type> MSHR;
181  std::deque<mshr_type> inflight_writes;
182 
183  long operate() override final;
184 
185  void initialize() override final;
186  void begin_phase() override final;
187  void end_phase(unsigned cpu) override final;
188 
189  [[deprecated("get_occupancy() returns 0 for every input except 0 (MSHR). Use get_mshr_occupancy() instead.")]] std::size_t get_occupancy(uint8_t queue_type,
190  uint64_t address);
191  [[deprecated("get_size() returns 0 for every input except 0 (MSHR). Use get_mshr_size() instead.")]] std::size_t get_size(uint8_t queue_type,
192  uint64_t address);
193 
194  std::size_t get_mshr_occupancy() const;
195  std::size_t get_mshr_size() const;
196  double get_mshr_occupancy_ratio() const;
197 
198  std::vector<std::size_t> get_rq_occupancy() const;
199  std::vector<std::size_t> get_rq_size() const;
200  std::vector<double> get_rq_occupancy_ratio() const;
201 
202  std::vector<std::size_t> get_wq_occupancy() const;
203  std::vector<std::size_t> get_wq_size() const;
204  std::vector<double> get_wq_occupancy_ratio() const;
205 
206  std::vector<std::size_t> get_pq_occupancy() const;
207  std::vector<std::size_t> get_pq_size() const;
208  std::vector<double> get_pq_occupancy_ratio() const;
209 
210  [[deprecated("Use get_set_index() instead.")]] uint64_t get_set(uint64_t address) const;
211  [[deprecated("This function should not be used to access the blocks directly.")]] uint64_t get_way(uint64_t address, uint64_t set) const;
212 
213  uint64_t invalidate_entry(uint64_t inval_addr);
214  int prefetch_line(uint64_t pf_addr, bool fill_this_level, uint32_t prefetch_metadata);
215 
216  [[deprecated("Use CACHE::prefetch_line(pf_addr, fill_this_level, prefetch_metadata) instead.")]] int
217  prefetch_line(uint64_t ip, uint64_t base_addr, uint64_t pf_addr, bool fill_this_level, uint32_t prefetch_metadata);
218 
219  void print_deadlock() override;
220 
221 #include "cache_module_decl.inc"
222 
223  struct module_concept {
224  virtual ~module_concept() = default;
225 
226  virtual void impl_prefetcher_initialize() = 0;
227  virtual uint32_t impl_prefetcher_cache_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, bool useful_prefetch, uint8_t type, uint32_t metadata_in) = 0;
228  virtual uint32_t impl_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in) = 0;
229  virtual void impl_prefetcher_cycle_operate() = 0;
230  virtual void impl_prefetcher_final_stats() = 0;
231  virtual void impl_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target) = 0;
232 
233  virtual void impl_initialize_replacement() = 0;
234  virtual uint32_t impl_find_victim(uint32_t triggering_cpu, uint64_t instr_id, uint32_t set, const BLOCK* current_set, uint64_t ip, uint64_t full_addr,
235  uint32_t type) = 0;
236  virtual void impl_update_replacement_state(uint32_t triggering_cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr,
237  uint32_t type, uint8_t hit) = 0;
238  virtual void impl_replacement_final_stats() = 0;
239  };
240 
241  template <unsigned long long P_FLAG, unsigned long long R_FLAG>
242  struct module_model final : module_concept {
244  explicit module_model(CACHE* cache) : intern_(cache) {}
245 
247  uint32_t impl_prefetcher_cache_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, bool useful_prefetch, uint8_t type, uint32_t metadata_in);
248  uint32_t impl_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in);
251  void impl_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target);
252 
254  uint32_t impl_find_victim(uint32_t triggering_cpu, uint64_t instr_id, uint32_t set, const BLOCK* current_set, uint64_t ip, uint64_t full_addr,
255  uint32_t type);
256  void impl_update_replacement_state(uint32_t triggering_cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr,
257  uint32_t type, uint8_t hit);
259  };
260 
261  std::unique_ptr<module_concept> module_pimpl;
262 
263  void impl_prefetcher_initialize() { module_pimpl->impl_prefetcher_initialize(); }
264  uint32_t impl_prefetcher_cache_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, bool useful_prefetch, uint8_t type, uint32_t metadata_in)
265  {
266  return module_pimpl->impl_prefetcher_cache_operate(addr, ip, cache_hit, useful_prefetch, type, metadata_in);
267  }
268  uint32_t impl_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
269  {
270  return module_pimpl->impl_prefetcher_cache_fill(addr, set, way, prefetch, evicted_addr, metadata_in);
271  }
272  void impl_prefetcher_cycle_operate() { module_pimpl->impl_prefetcher_cycle_operate(); }
273  void impl_prefetcher_final_stats() { module_pimpl->impl_prefetcher_final_stats(); }
274  void impl_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
275  {
276  module_pimpl->impl_prefetcher_branch_operate(ip, branch_type, branch_target);
277  }
278 
279  void impl_initialize_replacement() { module_pimpl->impl_initialize_replacement(); }
280  uint32_t impl_find_victim(uint32_t triggering_cpu, uint64_t instr_id, uint32_t set, const BLOCK* current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
281  {
282  return module_pimpl->impl_find_victim(triggering_cpu, instr_id, set, current_set, ip, full_addr, type);
283  }
284  void impl_update_replacement_state(uint32_t triggering_cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type,
285  uint8_t hit)
286  {
287  module_pimpl->impl_update_replacement_state(triggering_cpu, set, way, full_addr, ip, victim_addr, type, hit);
288  }
289  void impl_replacement_final_stats() { module_pimpl->impl_replacement_final_stats(); }
290 
292  {
293  };
294  template <unsigned long long P_FLAG = 0, unsigned long long R_FLAG = 0>
295  class Builder
296  {
298 
299  std::string m_name{};
300  double m_freq_scale{};
301  uint32_t m_sets{};
302  uint32_t m_ways{};
303  std::size_t m_pq_size{std::numeric_limits<std::size_t>::max()};
304  uint32_t m_mshr_size{};
305  uint64_t m_hit_lat{};
306  uint64_t m_fill_lat{};
307  uint64_t m_latency{};
308  uint32_t m_max_tag{};
309  uint32_t m_max_fill{};
310  unsigned m_offset_bits{};
311  bool m_pref_load{};
313  bool m_va_pref{};
314 
315  unsigned m_pref_act_mask{};
316  std::vector<CACHE::channel_type*> m_uls{};
319 
320  friend class CACHE;
321 
322  template <unsigned long long OTHER_P, unsigned long long OTHER_R>
324  : m_name(other.m_name), m_freq_scale(other.m_freq_scale), m_sets(other.m_sets), m_ways(other.m_ways), m_pq_size(other.m_pq_size),
327  m_va_pref(other.m_va_pref), m_pref_act_mask(other.m_pref_act_mask), m_uls(other.m_uls), m_ll(other.m_ll), m_lt(other.m_lt)
328  {
329  }
330 
331  public:
332  Builder() = default;
333 
334  self_type& name(std::string name_)
335  {
336  m_name = name_;
337  return *this;
338  }
339  self_type& frequency(double freq_scale_)
340  {
341  m_freq_scale = freq_scale_;
342  return *this;
343  }
344  self_type& sets(uint32_t sets_)
345  {
346  m_sets = sets_;
347  return *this;
348  }
349  self_type& ways(uint32_t ways_)
350  {
351  m_ways = ways_;
352  return *this;
353  }
354  self_type& pq_size(uint32_t pq_size_)
355  {
356  m_pq_size = pq_size_;
357  return *this;
358  }
359  self_type& mshr_size(uint32_t mshr_size_)
360  {
361  m_mshr_size = mshr_size_;
362  return *this;
363  }
364  self_type& latency(uint64_t lat_)
365  {
366  m_latency = lat_;
367  return *this;
368  }
369  self_type& hit_latency(uint64_t hit_lat_)
370  {
371  m_hit_lat = hit_lat_;
372  return *this;
373  }
374  self_type& fill_latency(uint64_t fill_lat_)
375  {
376  m_fill_lat = fill_lat_;
377  return *this;
378  }
379  self_type& tag_bandwidth(uint32_t max_read_)
380  {
381  m_max_tag = max_read_;
382  return *this;
383  }
384  self_type& fill_bandwidth(uint32_t max_write_)
385  {
386  m_max_fill = max_write_;
387  return *this;
388  }
389  self_type& offset_bits(unsigned offset_bits_)
390  {
391  m_offset_bits = offset_bits_;
392  return *this;
393  }
395  {
396  m_pref_load = true;
397  return *this;
398  }
400  {
401  m_pref_load = false;
402  return *this;
403  }
405  {
406  m_wq_full_addr = true;
407  return *this;
408  }
410  {
411  m_wq_full_addr = false;
412  return *this;
413  }
415  {
416  m_va_pref = true;
417  return *this;
418  }
420  {
421  m_va_pref = false;
422  return *this;
423  }
424  template <typename... Elems>
425  self_type& prefetch_activate(Elems... pref_act_elems)
426  {
427  m_pref_act_mask = ((1u << champsim::to_underlying(pref_act_elems)) | ... | 0);
428  return *this;
429  }
430  self_type& upper_levels(std::vector<CACHE::channel_type*>&& uls_)
431  {
432  m_uls = std::move(uls_);
433  return *this;
434  }
436  {
437  m_ll = ll_;
438  return *this;
439  }
441  {
442  m_lt = lt_;
443  return *this;
444  }
445  template <unsigned long long P>
447  {
449  }
450  template <unsigned long long R>
452  {
454  }
455  };
456 
457  template <unsigned long long P_FLAG, unsigned long long R_FLAG>
459  : champsim::operable(b.m_freq_scale), upper_levels(std::move(b.m_uls)), lower_level(b.m_ll), lower_translate(b.m_lt), NAME(b.m_name), NUM_SET(b.m_sets),
460  NUM_WAY(b.m_ways), MSHR_SIZE(b.m_mshr_size), PQ_SIZE(b.m_pq_size), HIT_LATENCY((b.m_hit_lat > 0) ? b.m_hit_lat : b.m_latency - b.m_fill_lat),
461  FILL_LATENCY(b.m_fill_lat), OFFSET_BITS(b.m_offset_bits), MAX_TAG(b.m_max_tag), MAX_FILL(b.m_max_fill), prefetch_as_load(b.m_pref_load),
462  match_offset_bits(b.m_wq_full_addr), virtual_prefetch(b.m_va_pref), pref_activate_mask(b.m_pref_act_mask),
463  module_pimpl(std::make_unique<module_model<P_FLAG, R_FLAG>>(this))
464  {
465  }
466 };
467 
468 #include "cache_module_def.inc"
469 
470 #endif
471 
472 #ifdef SET_ASIDE_CHAMPSIM_MODULE
473 #undef SET_ASIDE_CHAMPSIM_MODULE
474 #define CHAMPSIM_MODULE
475 #endif
access_type
Definition: channel.h:31
Definition: cache.h:296
self_type & pq_size(uint32_t pq_size_)
Definition: cache.h:354
self_type & prefetch_activate(Elems... pref_act_elems)
Definition: cache.h:425
self_type & set_virtual_prefetch()
Definition: cache.h:414
uint64_t m_hit_lat
Definition: cache.h:305
self_type & ways(uint32_t ways_)
Definition: cache.h:349
std::string m_name
Definition: cache.h:299
unsigned m_offset_bits
Definition: cache.h:310
std::size_t m_pq_size
Definition: cache.h:303
self_type & offset_bits(unsigned offset_bits_)
Definition: cache.h:389
self_type & hit_latency(uint64_t hit_lat_)
Definition: cache.h:369
unsigned m_pref_act_mask
Definition: cache.h:315
Builder()=default
self_type & fill_latency(uint64_t fill_lat_)
Definition: cache.h:374
bool m_wq_full_addr
Definition: cache.h:312
CACHE::channel_type * m_lt
Definition: cache.h:318
self_type & sets(uint32_t sets_)
Definition: cache.h:344
self_type & lower_translate(CACHE::channel_type *lt_)
Definition: cache.h:440
Builder(builder_conversion_tag, const Builder< OTHER_P, OTHER_R > &other)
Definition: cache.h:323
uint32_t m_max_fill
Definition: cache.h:309
uint32_t m_max_tag
Definition: cache.h:308
Builder< P_FLAG, R > replacement()
Definition: cache.h:451
self_type & name(std::string name_)
Definition: cache.h:334
self_type & reset_wq_checks_full_addr()
Definition: cache.h:409
self_type & mshr_size(uint32_t mshr_size_)
Definition: cache.h:359
self_type & reset_virtual_prefetch()
Definition: cache.h:419
uint32_t m_sets
Definition: cache.h:301
CACHE::channel_type * m_ll
Definition: cache.h:317
uint64_t m_fill_lat
Definition: cache.h:306
bool m_va_pref
Definition: cache.h:313
self_type & upper_levels(std::vector< CACHE::channel_type * > &&uls_)
Definition: cache.h:430
Builder< P, R_FLAG > prefetcher()
Definition: cache.h:446
self_type & lower_level(CACHE::channel_type *ll_)
Definition: cache.h:435
self_type & frequency(double freq_scale_)
Definition: cache.h:339
self_type & fill_bandwidth(uint32_t max_write_)
Definition: cache.h:384
self_type & reset_prefetch_as_load()
Definition: cache.h:399
self_type & latency(uint64_t lat_)
Definition: cache.h:364
self_type & set_prefetch_as_load()
Definition: cache.h:394
uint32_t m_mshr_size
Definition: cache.h:304
uint64_t m_latency
Definition: cache.h:307
double m_freq_scale
Definition: cache.h:300
self_type & set_wq_checks_full_addr()
Definition: cache.h:404
self_type & tag_bandwidth(uint32_t max_read_)
Definition: cache.h:379
std::vector< CACHE::channel_type * > m_uls
Definition: cache.h:316
bool m_pref_load
Definition: cache.h:311
uint32_t m_ways
Definition: cache.h:302
Definition: cache.h:292
Definition: cache.h:57
std::vector< std::size_t > get_wq_size() const
Definition: cache.cc:629
const bool match_offset_bits
Definition: cache.h:171
const uint64_t HIT_LATENCY
Definition: cache.h:166
void impl_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
Definition: cache.h:274
const std::size_t PQ_SIZE
Definition: cache.h:165
set_type block
Definition: cache.h:168
std::vector< double > get_pq_occupancy_ratio() const
Definition: cache.cc:671
void impl_initialize_replacement()
Definition: cache.h:279
std::deque< tag_lookup_type > translation_stash
Definition: cache.h:155
const unsigned pref_activate_mask
Definition: cache.h:174
const uint32_t MSHR_SIZE
Definition: cache.h:164
const uint32_t NUM_SET
Definition: cache.h:164
std::size_t get_mshr_size() const
Definition: cache.cc:620
bool handle_write(const tag_lookup_type &handle_pkt)
Definition: cache.cc:294
std::deque< mshr_type > MSHR
Definition: cache.h:180
std::deque< mshr_type > inflight_writes
Definition: cache.h:181
std::vector< std::size_t > get_wq_occupancy() const
Definition: cache.cc:596
bool handle_fill(const mshr_type &fill_mshr)
Definition: cache.cc:82
uint32_t impl_prefetcher_cache_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, bool useful_prefetch, uint8_t type, uint32_t metadata_in)
Definition: cache.h:264
channel_type * lower_translate
Definition: cache.h:160
std::size_t get_size(uint8_t queue_type, uint64_t address)
Definition: cache.cc:645
std::deque< tag_lookup_type > internal_PQ
Definition: cache.h:153
typename channel_type::response_type response_type
Definition: cache.h:64
std::size_t get_set_index(uint64_t address) const
Definition: cache.cc:426
typename channel_type::request_type request_type
Definition: cache.h:63
bool handle_miss(const tag_lookup_type &handle_pkt)
Definition: cache.cc:215
void impl_replacement_final_stats()
Definition: cache.h:289
std::size_t get_mshr_occupancy() const
Definition: cache.cc:587
void finish_translation(const response_type &packet)
Definition: cache.cc:527
const std::string NAME
Definition: cache.h:163
long operate() override final
Definition: cache.cc:331
uint64_t invalidate_entry(uint64_t inval_addr)
Definition: cache.cc:458
uint64_t get_set(uint64_t address) const
Definition: cache.cc:423
std::pair< set_type::iterator, set_type::iterator > get_set_span(uint64_t address)
Definition: cache.cc:435
void finish_packet(const response_type &packet)
Definition: cache.cc:498
uint64_t get_way(uint64_t address, uint64_t set) const
Definition: cache.cc:450
const long int MAX_FILL
Definition: cache.h:169
bool try_hit(const tag_lookup_type &handle_pkt)
Definition: cache.cc:167
channel_type * lower_level
Definition: cache.h:159
void initialize() override final
Definition: cache.cc:673
uint32_t cpu
Definition: cache.h:162
bool ever_seen_data
Definition: cache.h:173
void issue_translation()
Definition: cache.cc:554
const long int MAX_TAG
Definition: cache.h:169
void impl_prefetcher_final_stats()
Definition: cache.h:273
stats_type roi_stats
Definition: cache.h:178
void end_phase(unsigned cpu) override final
Definition: cache.cc:696
std::unique_ptr< module_concept > module_pimpl
Definition: cache.h:261
int prefetch_line(uint64_t pf_addr, bool fill_this_level, uint32_t prefetch_metadata)
Definition: cache.cc:470
void print_deadlock() override
Definition: cache.cc:742
std::vector< BLOCK > set_type
Definition: cache.h:141
auto initiate_tag_check(champsim::channel *ul=nullptr)
Definition: cache.cc:311
const uint32_t NUM_WAY
Definition: cache.h:164
std::vector< double > get_wq_occupancy_ratio() const
Definition: cache.cc:669
std::vector< double > get_rq_occupancy_ratio() const
Definition: cache.cc:667
std::size_t get_occupancy(uint8_t queue_type, uint64_t address)
Definition: cache.cc:612
FILL_LEVEL
Definition: cache.h:59
@ FILL_DRAM
Definition: cache.h:60
@ FILL_LLC
Definition: cache.h:60
@ FILL_L2
Definition: cache.h:60
@ FILL_L1
Definition: cache.h:60
@ FILL_DRC
Definition: cache.h:60
void impl_update_replacement_state(uint32_t triggering_cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)
Definition: cache.h:284
const bool virtual_prefetch
Definition: cache.h:172
std::vector< std::size_t > get_pq_size() const
Definition: cache.cc:636
bool should_activate_prefetcher(const T &pkt) const
Definition: cache.cc:736
std::vector< std::size_t > get_rq_size() const
Definition: cache.cc:622
CACHE(Builder< P_FLAG, R_FLAG > b)
Definition: cache.h:458
std::vector< std::size_t > get_pq_occupancy() const
Definition: cache.cc:603
void impl_prefetcher_initialize()
Definition: cache.h:263
const bool prefetch_as_load
Definition: cache.h:170
stats_type sim_stats
Definition: cache.h:178
void impl_prefetcher_cycle_operate()
Definition: cache.h:272
std::deque< tag_lookup_type > inflight_tag_check
Definition: cache.h:154
uint32_t impl_find_victim(uint32_t triggering_cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
Definition: cache.h:280
const unsigned OFFSET_BITS
Definition: cache.h:167
void begin_phase() override final
Definition: cache.cc:679
double get_mshr_occupancy_ratio() const
Definition: cache.cc:665
std::vector< channel_type * > upper_levels
Definition: cache.h:158
uint32_t impl_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
Definition: cache.h:268
std::vector< std::size_t > get_rq_occupancy() const
Definition: cache.cc:589
const uint64_t FILL_LATENCY
Definition: cache.h:166
Definition: channel.h:64
response response_type
Definition: channel.h:109
request request_type
Definition: channel.h:110
Definition: operable.h:24
operable(double scale)
Definition: operable.h:32
branch_type
Definition: instruction.h:30
Definition: champsim.h:24
constexpr std::underlying_type_t< E > to_underlying(E e) noexcept
Definition: bits.h:40
Definition: cache.h:127
uint64_t data
Definition: cache.h:134
bool dirty
Definition: cache.h:130
bool prefetch
Definition: cache.h:129
bool valid
Definition: cache.h:128
uint32_t pf_metadata
Definition: cache.h:136
uint64_t v_address
Definition: cache.h:133
BLOCK()=default
uint64_t address
Definition: cache.h:132
Definition: cache.h:223
virtual void impl_update_replacement_state(uint32_t triggering_cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)=0
virtual void impl_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)=0
virtual void impl_replacement_final_stats()=0
virtual void impl_initialize_replacement()=0
virtual uint32_t impl_prefetcher_cache_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, bool useful_prefetch, uint8_t type, uint32_t metadata_in)=0
virtual void impl_prefetcher_initialize()=0
virtual ~module_concept()=default
virtual void impl_prefetcher_cycle_operate()=0
virtual uint32_t impl_find_victim(uint32_t triggering_cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)=0
virtual void impl_prefetcher_final_stats()=0
virtual uint32_t impl_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)=0
Definition: cache.h:242
void impl_prefetcher_final_stats()
CACHE * intern_
Definition: cache.h:243
uint32_t impl_find_victim(uint32_t triggering_cpu, uint64_t instr_id, uint32_t set, const BLOCK *current_set, uint64_t ip, uint64_t full_addr, uint32_t type)
void impl_update_replacement_state(uint32_t triggering_cpu, uint32_t set, uint32_t way, uint64_t full_addr, uint64_t ip, uint64_t victim_addr, uint32_t type, uint8_t hit)
uint32_t impl_prefetcher_cache_operate(uint64_t addr, uint64_t ip, uint8_t cache_hit, bool useful_prefetch, uint8_t type, uint32_t metadata_in)
void impl_initialize_replacement()
void impl_prefetcher_initialize()
void impl_prefetcher_cycle_operate()
uint32_t impl_prefetcher_cache_fill(uint64_t addr, uint32_t set, uint32_t way, uint8_t prefetch, uint64_t evicted_addr, uint32_t metadata_in)
void impl_replacement_final_stats()
module_model(CACHE *cache)
Definition: cache.h:244
void impl_prefetcher_branch_operate(uint64_t ip, uint8_t branch_type, uint64_t branch_target)
Definition: cache.h:93
uint32_t pf_metadata
Definition: cache.h:100
access_type type
Definition: cache.h:103
uint64_t ip
Definition: cache.h:97
bool prefetch_from_this
Definition: cache.h:104
static mshr_type merge(mshr_type predecessor, mshr_type successor)
Definition: cache.cc:47
std::vector< std::reference_wrapper< ooo_model_instr > > instr_depend_on_me
Definition: cache.h:111
uint64_t instr_id
Definition: cache.h:98
uint32_t cpu
Definition: cache.h:101
mshr_type(tag_lookup_type req, uint64_t cycle)
Definition: cache.cc:41
uint64_t address
Definition: cache.h:94
uint8_t asid[2]
Definition: cache.h:106
uint64_t cycle_enqueued
Definition: cache.h:109
uint64_t event_cycle
Definition: cache.h:108
uint64_t v_address
Definition: cache.h:95
uint64_t data
Definition: cache.h:96
std::vector< std::deque< response_type > * > to_return
Definition: cache.h:112
Definition: cache.h:66
uint64_t data
Definition: cache.h:69
tag_lookup_type(request_type req)
Definition: cache.h:89
uint32_t cpu
Definition: cache.h:74
uint64_t address
Definition: cache.h:67
bool skip_fill
Definition: cache.h:78
uint64_t v_address
Definition: cache.h:68
uint32_t pf_metadata
Definition: cache.h:73
uint64_t instr_id
Definition: cache.h:71
uint64_t event_cycle
Definition: cache.h:84
bool is_translated
Definition: cache.h:79
std::vector< std::deque< response_type > * > to_return
Definition: cache.h:87
bool translate_issued
Definition: cache.h:80
std::vector< std::reference_wrapper< ooo_model_instr > > instr_depend_on_me
Definition: cache.h:86
uint64_t ip
Definition: cache.h:70
uint8_t asid[2]
Definition: cache.h:82
bool prefetch_from_this
Definition: cache.h:77
access_type type
Definition: cache.h:76
Definition: cache.h:40
double avg_miss_latency
Definition: cache.h:52
uint64_t pf_fill
Definition: cache.h:47
uint64_t pf_useless
Definition: cache.h:46
std::array< std::array< uint64_t, NUM_CPUS >, champsim::to_underlying(access_type::NUM_TYPES)> hits
Definition: cache.h:49
std::string name
Definition: cache.h:41
uint64_t pf_useful
Definition: cache.h:45
uint64_t pf_requested
Definition: cache.h:43
std::array< std::array< uint64_t, NUM_CPUS >, champsim::to_underlying(access_type::NUM_TYPES)> misses
Definition: cache.h:50
uint64_t total_miss_latency
Definition: cache.h:53
uint64_t pf_issued
Definition: cache.h:44