O3_CPU Class Reference

#include <ooo_cpu.h>

Inheritance diagram for O3_CPU:

Collaboration diagram for O3_CPU:

Classes
class	Builder
class	builder_conversion_tag
struct	dib_shift
struct	module_concept
struct	module_model

Public Types
using	stats_type = cpu_stats
using	dib_type = champsim::lru_table< uint64_t, dib_shift, dib_shift >

Public Member Functions
void	initialize () override final
long	operate () override final
void	begin_phase () override final
void	end_phase (unsigned cpu) override final
void	initialize_instruction ()
long	check_dib ()
long	fetch_instruction ()
long	promote_to_decode ()
long	decode_instruction ()
long	dispatch_instruction ()
long	schedule_instruction ()
long	execute_instruction ()
long	operate_lsq ()
long	complete_inflight_instruction ()
long	handle_memory_return ()
long	retire_rob ()
bool	do_init_instruction (ooo_model_instr &instr)
bool	do_predict_branch (ooo_model_instr &instr)
void	do_check_dib (ooo_model_instr &instr)
bool	do_fetch_instruction (std::deque< ooo_model_instr >::iterator begin, std::deque< ooo_model_instr >::iterator end)
void	do_dib_update (const ooo_model_instr &instr)
void	do_scheduling (ooo_model_instr &instr)
void	do_execution (ooo_model_instr &rob_it)
void	do_memory_scheduling (ooo_model_instr &instr)
void	do_complete_execution (ooo_model_instr &instr)
void	do_sq_forward_to_lq (LSQ_ENTRY &sq_entry, LSQ_ENTRY &lq_entry)
void	do_finish_store (const LSQ_ENTRY &sq_entry)
bool	do_complete_store (const LSQ_ENTRY &sq_entry)
bool	execute_load (const LSQ_ENTRY &lq_entry)
uint64_t	roi_instr () const
uint64_t	roi_cycle () const
uint64_t	sim_instr () const
uint64_t	sim_cycle () const
void	print_deadlock () override final
void	impl_initialize_branch_predictor ()
void	impl_last_branch_result (uint64_t ip, uint64_t target, uint8_t taken, uint8_t branch_type)
uint8_t	impl_predict_branch (uint64_t ip)
void	impl_initialize_btb ()
void	impl_update_btb (uint64_t ip, uint64_t predicted_target, uint8_t taken, uint8_t branch_type)
std::pair< uint64_t, uint8_t >	impl_btb_prediction (uint64_t ip)
template<unsigned long long B_FLAG, unsigned long long T_FLAG>
	O3_CPU (Builder< B_FLAG, T_FLAG > b)
Public Member Functions inherited from champsim::operable
	operable (double scale)
long	_operate ()

Public Attributes
uint32_t	cpu = 0
uint64_t	begin_phase_cycle = 0
uint64_t	begin_phase_instr = 0
uint64_t	finish_phase_cycle = 0
uint64_t	finish_phase_instr = 0
uint64_t	last_heartbeat_cycle = 0
uint64_t	last_heartbeat_instr = 0
uint64_t	next_print_instruction = STAT_PRINTING_PERIOD
uint64_t	num_retired = 0
uint64_t	num_base_update_uops = 0
bool	show_heartbeat = true
stats_type	roi_stats {}
stats_type	sim_stats {}
dib_type	DIB
std::deque< ooo_model_instr >	IFETCH_BUFFER
std::deque< ooo_model_instr >	DISPATCH_BUFFER
std::deque< ooo_model_instr >	DECODE_BUFFER
std::deque< ooo_model_instr >	ROB
std::vector< std::optional< LSQ_ENTRY > >	LQ
std::deque< LSQ_ENTRY >	SQ
std::array< std::vector< std::reference_wrapper< ooo_model_instr > >, std::numeric_limits< uint8_t >::max()+1 >	reg_producers
const std::size_t	IFETCH_BUFFER_SIZE
const std::size_t	DISPATCH_BUFFER_SIZE
const std::size_t	DECODE_BUFFER_SIZE
const std::size_t	ROB_SIZE
const std::size_t	SQ_SIZE
const long int	FETCH_WIDTH
const long int	DECODE_WIDTH
const long int	DISPATCH_WIDTH
const long int	SCHEDULER_SIZE
const long int	EXEC_WIDTH
const long int	LQ_WIDTH
const long int	SQ_WIDTH
const long int	RETIRE_WIDTH
const unsigned	BRANCH_MISPREDICT_PENALTY
const unsigned	DISPATCH_LATENCY
const unsigned	DECODE_LATENCY
const unsigned	SCHEDULING_LATENCY
const unsigned	EXEC_LATENCY
const long int	L1I_BANDWIDTH
const long int	L1D_BANDWIDTH
uint64_t	fetch_resume_cycle = 0
const long	IN_QUEUE_SIZE = 2 * FETCH_WIDTH
std::deque< ooo_model_instr >	input_queue
CacheBus	L1I_bus
CacheBus	L1D_bus
CACHE *	l1i
std::unique_ptr< module_concept >	module_pimpl
Public Attributes inherited from champsim::operable
const double	CLOCK_SCALE
double	leap_operation = 0
uint64_t	current_cycle = 0
bool	warmup = true

Member Typedef Documentation

dib_type

using O3_CPU::dib_type = champsim::lru_table<uint64_t, dib_shift, dib_shift>

stats_type

using O3_CPU::stats_type = cpu_stats

Constructor & Destructor Documentation

O3_CPU()

template<unsigned long long B_FLAG, unsigned long long T_FLAG>

O3_CPU::O3_CPU ( Builder< B_FLAG, T_FLAG >  b )

inlineexplicit

Member Function Documentation

begin_phase()

void O3_CPU::begin_phase ( )

finaloverridevirtual

Reimplemented from champsim::operable.

check_dib()

long O3_CPU::check_dib

(

)

complete_inflight_instruction()

long O3_CPU::complete_inflight_instruction

(

)

decode_instruction()

long O3_CPU::decode_instruction

(

)

dispatch_instruction()

long O3_CPU::dispatch_instruction

(

)

do_check_dib()

void O3_CPU::do_check_dib

(

ooo_model_instr &

instr

)

do_complete_execution()

void O3_CPU::do_complete_execution

(

ooo_model_instr &

instr

)

do_complete_store()

bool O3_CPU::do_complete_store

(

const LSQ_ENTRY &

sq_entry

)

do_dib_update()

void O3_CPU::do_dib_update

(

const ooo_model_instr &

instr

)

do_execution()

void O3_CPU::do_execution

(

ooo_model_instr &

rob_it

)

do_fetch_instruction()

bool O3_CPU::do_fetch_instruction	(	std::deque< ooo_model_instr >::iterator	begin,
		std::deque< ooo_model_instr >::iterator	end
	)

do_finish_store()

void O3_CPU::do_finish_store

(

const LSQ_ENTRY &

sq_entry

)

do_init_instruction()

bool O3_CPU::do_init_instruction

(

ooo_model_instr &

instr

)

do_memory_scheduling()

void O3_CPU::do_memory_scheduling

(

ooo_model_instr &

instr

)

do_predict_branch()

bool O3_CPU::do_predict_branch

(

ooo_model_instr &

instr

)

do_scheduling()

void O3_CPU::do_scheduling

(

ooo_model_instr &

instr

)

do_sq_forward_to_lq()

void O3_CPU::do_sq_forward_to_lq	(	LSQ_ENTRY &	sq_entry,
		LSQ_ENTRY &	lq_entry
	)

end_phase()

void O3_CPU::end_phase ( unsigned  cpu )

finaloverridevirtual

Reimplemented from champsim::operable.

execute_instruction()

long O3_CPU::execute_instruction

(

)

execute_load()

bool O3_CPU::execute_load

(

const LSQ_ENTRY &

lq_entry

)

fetch_instruction()

long O3_CPU::fetch_instruction

(

)

handle_memory_return()

long O3_CPU::handle_memory_return

(

)

impl_btb_prediction()

std::pair<uint64_t, uint8_t> O3_CPU::impl_btb_prediction ( uint64_t  ip )

inline

impl_initialize_branch_predictor()

void O3_CPU::impl_initialize_branch_predictor ( )

inline

impl_initialize_btb()

void O3_CPU::impl_initialize_btb ( )

inline

impl_last_branch_result()

void O3_CPU::impl_last_branch_result ( uint64_t  ip, uint64_t  target, uint8_t  taken, uint8_t  branch_type  )

inline

impl_predict_branch()

uint8_t O3_CPU::impl_predict_branch ( uint64_t  ip )

inline

impl_update_btb()

void O3_CPU::impl_update_btb ( uint64_t  ip, uint64_t  predicted_target, uint8_t  taken, uint8_t  branch_type  )

inline

initialize()

void O3_CPU::initialize ( )

finaloverridevirtual

Reimplemented from champsim::operable.

initialize_instruction()

void O3_CPU::initialize_instruction

(

)

operate()

long O3_CPU::operate ( )

finaloverridevirtual

Implements champsim::operable.

operate_lsq()

long O3_CPU::operate_lsq

(

)

print_deadlock()

void O3_CPU::print_deadlock ( )

finaloverridevirtual

Reimplemented from champsim::operable.

promote_to_decode()

long O3_CPU::promote_to_decode

(

)

retire_rob()

long O3_CPU::retire_rob

(

)

roi_cycle()

uint64_t O3_CPU::roi_cycle ( ) const

inline

roi_instr()

uint64_t O3_CPU::roi_instr ( ) const

inline

schedule_instruction()

long O3_CPU::schedule_instruction

(

)

sim_cycle()

uint64_t O3_CPU::sim_cycle ( ) const

inline

sim_instr()

uint64_t O3_CPU::sim_instr ( ) const

inline

Member Data Documentation

begin_phase_cycle

uint64_t O3_CPU::begin_phase_cycle = 0

begin_phase_instr

uint64_t O3_CPU::begin_phase_instr = 0

BRANCH_MISPREDICT_PENALTY

const unsigned O3_CPU::BRANCH_MISPREDICT_PENALTY

cpu

uint32_t O3_CPU::cpu = 0

DECODE_BUFFER

std::deque<ooo_model_instr> O3_CPU::DECODE_BUFFER

DECODE_BUFFER_SIZE

const std::size_t O3_CPU::DECODE_BUFFER_SIZE

DECODE_LATENCY

const unsigned O3_CPU::DECODE_LATENCY

DECODE_WIDTH

const long int O3_CPU::DECODE_WIDTH

DIB

dib_type O3_CPU::DIB

DISPATCH_BUFFER

std::deque<ooo_model_instr> O3_CPU::DISPATCH_BUFFER

DISPATCH_BUFFER_SIZE

const std::size_t O3_CPU::DISPATCH_BUFFER_SIZE

DISPATCH_LATENCY

const unsigned O3_CPU::DISPATCH_LATENCY

DISPATCH_WIDTH

const long int O3_CPU::DISPATCH_WIDTH

EXEC_LATENCY

const unsigned O3_CPU::EXEC_LATENCY

EXEC_WIDTH

const long int O3_CPU::EXEC_WIDTH

fetch_resume_cycle

uint64_t O3_CPU::fetch_resume_cycle = 0

FETCH_WIDTH

const long int O3_CPU::FETCH_WIDTH

finish_phase_cycle

uint64_t O3_CPU::finish_phase_cycle = 0

finish_phase_instr

uint64_t O3_CPU::finish_phase_instr = 0

IFETCH_BUFFER

std::deque<ooo_model_instr> O3_CPU::IFETCH_BUFFER

IFETCH_BUFFER_SIZE

const std::size_t O3_CPU::IFETCH_BUFFER_SIZE

IN_QUEUE_SIZE

const long O3_CPU::IN_QUEUE_SIZE = 2 * FETCH_WIDTH

input_queue

std::deque<ooo_model_instr> O3_CPU::input_queue

L1D_BANDWIDTH

const long int O3_CPU::L1D_BANDWIDTH

L1D_bus

CacheBus O3_CPU::L1D_bus

l1i

CACHE* O3_CPU::l1i

L1I_BANDWIDTH

const long int O3_CPU::L1I_BANDWIDTH

L1I_bus

CacheBus O3_CPU::L1I_bus

last_heartbeat_cycle

uint64_t O3_CPU::last_heartbeat_cycle = 0

last_heartbeat_instr

uint64_t O3_CPU::last_heartbeat_instr = 0

LQ

std::vector<std::optional<LSQ_ENTRY> > O3_CPU::LQ

LQ_WIDTH

const long int O3_CPU::LQ_WIDTH

module_pimpl

std::unique_ptr<module_concept> O3_CPU::module_pimpl

next_print_instruction

uint64_t O3_CPU::next_print_instruction = STAT_PRINTING_PERIOD

num_base_update_uops

uint64_t O3_CPU::num_base_update_uops = 0

num_retired

uint64_t O3_CPU::num_retired = 0

reg_producers

std::array<std::vector<std::reference_wrapper<ooo_model_instr> >, std::numeric_limits<uint8_t>::max() + 1> O3_CPU::reg_producers

RETIRE_WIDTH

const long int O3_CPU::RETIRE_WIDTH

ROB

std::deque<ooo_model_instr> O3_CPU::ROB

ROB_SIZE

const std::size_t O3_CPU::ROB_SIZE

roi_stats

stats_type O3_CPU::roi_stats {}

SCHEDULER_SIZE

const long int O3_CPU::SCHEDULER_SIZE

SCHEDULING_LATENCY

const unsigned O3_CPU::SCHEDULING_LATENCY

show_heartbeat

bool O3_CPU::show_heartbeat = true

sim_stats

stats_type O3_CPU::sim_stats {}

SQ

std::deque<LSQ_ENTRY> O3_CPU::SQ

SQ_SIZE

const std::size_t O3_CPU::SQ_SIZE

SQ_WIDTH

const long int O3_CPU::SQ_WIDTH

---

The documentation for this class was generated from the following files:

• inc/ooo_cpu.h
• src/ooo_cpu.cc