ChampSim
Variables
champsim::defaults Namespace Reference

Variables

const auto default_core
 
const auto default_l1i
 
const auto default_l1d
 
const auto default_l2c
 
const auto default_itlb
 
const auto default_dtlb
 
const auto default_stlb
 
const auto default_llc
 
const auto default_ptw
 

Variable Documentation

◆ default_core

const auto champsim::defaults::default_core
Initial value:
= O3_CPU::Builder{}
.dib_set(32)
.dib_way(8)
.dib_window(16)
.ifetch_buffer_size(64)
.decode_buffer_size(32)
.dispatch_buffer_size(32)
.rob_size(352)
.lq_size(128)
.sq_size(72)
.fetch_width(6)
.decode_width(6)
.dispatch_width(6)
.execute_width(4)
.lq_width(2)
.sq_width(2)
.retire_width(5)
.mispredict_penalty(1)
.schedule_width(128)
.decode_latency(1)
.dispatch_latency(1)
.schedule_latency(0)
.execute_latency(0)
.l1i_bandwidth(1)
.l1d_bandwidth(1)
.branch_predictor<O3_CPU::bbranchDbimodal>()
.btb<O3_CPU::tbtbDbasic_btb>()
O3_CPU::Builder
Definition: ooo_cpu.h:252
O3_CPU::Builder::l1d_bandwidth
self_type & l1d_bandwidth(long int l1d_bw_)
Definition: ooo_cpu.h:434
O3_CPU::Builder::dib_window
self_type & dib_window(std::size_t dib_window_)
Definition: ooo_cpu.h:324
O3_CPU::Builder::sq_size
self_type & sq_size(std::size_t sq_size_)
Definition: ooo_cpu.h:354
O3_CPU::Builder::schedule_latency
self_type & schedule_latency(unsigned schedule_latency_)
Definition: ooo_cpu.h:414
O3_CPU::Builder::lq_width
self_type & lq_width(unsigned lq_width_)
Definition: ooo_cpu.h:384
O3_CPU::Builder::ifetch_buffer_size
self_type & ifetch_buffer_size(std::size_t ifetch_buffer_size_)
Definition: ooo_cpu.h:329
O3_CPU::Builder::rob_size
self_type & rob_size(std::size_t rob_size_)
Definition: ooo_cpu.h:344
O3_CPU::Builder::mispredict_penalty
self_type & mispredict_penalty(unsigned mispredict_penalty_)
Definition: ooo_cpu.h:399
O3_CPU::Builder::dib_way
self_type & dib_way(std::size_t dib_way_)
Definition: ooo_cpu.h:319
O3_CPU::Builder::l1i_bandwidth
self_type & l1i_bandwidth(long int l1i_bw_)
Definition: ooo_cpu.h:429
O3_CPU::Builder::dib_set
self_type & dib_set(std::size_t dib_set_)
Definition: ooo_cpu.h:314
O3_CPU::Builder::dispatch_buffer_size
self_type & dispatch_buffer_size(std::size_t dispatch_buffer_size_)
Definition: ooo_cpu.h:339
O3_CPU::Builder::execute_width
self_type & execute_width(unsigned execute_width_)
Definition: ooo_cpu.h:379
O3_CPU::Builder::decode_width
self_type & decode_width(unsigned decode_width_)
Definition: ooo_cpu.h:364
O3_CPU::Builder::retire_width
self_type & retire_width(unsigned retire_width_)
Definition: ooo_cpu.h:394
O3_CPU::Builder::schedule_width
self_type & schedule_width(unsigned schedule_width_)
Definition: ooo_cpu.h:374
O3_CPU::Builder::fetch_width
self_type & fetch_width(unsigned fetch_width_)
Definition: ooo_cpu.h:359
O3_CPU::Builder::branch_predictor
Builder< B, T_FLAG > branch_predictor()
Definition: ooo_cpu.h:451
O3_CPU::Builder::decode_latency
self_type & decode_latency(unsigned decode_latency_)
Definition: ooo_cpu.h:404
O3_CPU::Builder::sq_width
self_type & sq_width(unsigned sq_width_)
Definition: ooo_cpu.h:389
O3_CPU::Builder::dispatch_width
self_type & dispatch_width(unsigned dispatch_width_)
Definition: ooo_cpu.h:369
O3_CPU::Builder::decode_buffer_size
self_type & decode_buffer_size(std::size_t decode_buffer_size_)
Definition: ooo_cpu.h:334
O3_CPU::Builder::execute_latency
self_type & execute_latency(unsigned execute_latency_)
Definition: ooo_cpu.h:419
O3_CPU::Builder::dispatch_latency
self_type & dispatch_latency(unsigned dispatch_latency_)
Definition: ooo_cpu.h:409
O3_CPU::Builder::lq_size
self_type & lq_size(std::size_t lq_size_)
Definition: ooo_cpu.h:349

◆ default_dtlb

const auto champsim::defaults::default_dtlb
Initial value:
= CACHE::Builder{}
.sets(16)
.ways(4)
.pq_size(0)
.mshr_size(8)
.hit_latency(1)
.fill_latency(1)
.tag_bandwidth(2)
.fill_bandwidth(2)
.offset_bits(LOG2_PAGE_SIZE)
.reset_prefetch_as_load()
.reset_virtual_prefetch()
.set_wq_checks_full_addr()
.prefetch_activate(access_type::LOAD, access_type::PREFETCH)
.prefetcher<CACHE::pprefetcherDno>()
.replacement<CACHE::rreplacementDlru>()
CACHE::Builder
Definition: cache.h:296
CACHE::Builder::pq_size
self_type & pq_size(uint32_t pq_size_)
Definition: cache.h:354
CACHE::Builder::prefetch_activate
self_type & prefetch_activate(Elems... pref_act_elems)
Definition: cache.h:425
CACHE::Builder::ways
self_type & ways(uint32_t ways_)
Definition: cache.h:349
CACHE::Builder::offset_bits
self_type & offset_bits(unsigned offset_bits_)
Definition: cache.h:389
CACHE::Builder::hit_latency
self_type & hit_latency(uint64_t hit_lat_)
Definition: cache.h:369
CACHE::Builder::fill_latency
self_type & fill_latency(uint64_t fill_lat_)
Definition: cache.h:374
CACHE::Builder::sets
self_type & sets(uint32_t sets_)
Definition: cache.h:344
CACHE::Builder::mshr_size
self_type & mshr_size(uint32_t mshr_size_)
Definition: cache.h:359
CACHE::Builder::reset_virtual_prefetch
self_type & reset_virtual_prefetch()
Definition: cache.h:419
CACHE::Builder::prefetcher
Builder< P, R_FLAG > prefetcher()
Definition: cache.h:446
CACHE::Builder::fill_bandwidth
self_type & fill_bandwidth(uint32_t max_write_)
Definition: cache.h:384
CACHE::Builder::reset_prefetch_as_load
self_type & reset_prefetch_as_load()
Definition: cache.h:399
CACHE::Builder::set_wq_checks_full_addr
self_type & set_wq_checks_full_addr()
Definition: cache.h:404
CACHE::Builder::tag_bandwidth
self_type & tag_bandwidth(uint32_t max_read_)
Definition: cache.h:379

◆ default_itlb

const auto champsim::defaults::default_itlb
Initial value:
= CACHE::Builder{}
.sets(16)
.ways(4)
.pq_size(0)
.mshr_size(8)
.hit_latency(1)
.fill_latency(1)
.tag_bandwidth(2)
.fill_bandwidth(2)
.offset_bits(LOG2_PAGE_SIZE)
.reset_prefetch_as_load()
.set_virtual_prefetch()
.set_wq_checks_full_addr()
.prefetch_activate(access_type::LOAD, access_type::PREFETCH)
.prefetcher<CACHE::pprefetcherDno>()
.replacement<CACHE::rreplacementDlru>()
CACHE::Builder::set_virtual_prefetch
self_type & set_virtual_prefetch()
Definition: cache.h:414

◆ default_l1d

const auto champsim::defaults::default_l1d
Initial value:
= CACHE::Builder{}
.sets(64)
.ways(12)
.pq_size(8)
.mshr_size(16)
.hit_latency(4)
.fill_latency(1)
.tag_bandwidth(2)
.fill_bandwidth(2)
.offset_bits(LOG2_BLOCK_SIZE)
.reset_prefetch_as_load()
.reset_virtual_prefetch()
.set_wq_checks_full_addr()
.prefetch_activate(access_type::LOAD, access_type::PREFETCH)
.prefetcher<CACHE::pprefetcherDno>()
.replacement<CACHE::rreplacementDlru>()

◆ default_l1i

const auto champsim::defaults::default_l1i
Initial value:
= CACHE::Builder{}
.sets(64)
.ways(8)
.pq_size(32)
.mshr_size(8)
.hit_latency(3)
.fill_latency(1)
.tag_bandwidth(2)
.fill_bandwidth(2)
.offset_bits(LOG2_BLOCK_SIZE)
.reset_prefetch_as_load()
.set_virtual_prefetch()
.set_wq_checks_full_addr()
.prefetch_activate(access_type::LOAD, access_type::PREFETCH)
.prefetcher<CACHE::pprefetcherDno_instr>()
.replacement<CACHE::rreplacementDlru>()

◆ default_l2c

const auto champsim::defaults::default_l2c
Initial value:
= CACHE::Builder{}
.sets(1024)
.ways(8)
.pq_size(16)
.mshr_size(32)
.hit_latency(9)
.fill_latency(1)
.tag_bandwidth(1)
.fill_bandwidth(1)
.offset_bits(LOG2_BLOCK_SIZE)
.reset_prefetch_as_load()
.reset_virtual_prefetch()
.reset_wq_checks_full_addr()
.prefetch_activate(access_type::LOAD, access_type::PREFETCH)
.prefetcher<CACHE::pprefetcherDno>()
.replacement<CACHE::rreplacementDlru>()
CACHE::Builder::reset_wq_checks_full_addr
self_type & reset_wq_checks_full_addr()
Definition: cache.h:409

◆ default_llc

const auto champsim::defaults::default_llc
Initial value:
= CACHE::Builder{}
.name("LLC")
.sets(2048 * NUM_CPUS)
.ways(16)
.pq_size(32 * NUM_CPUS)
.mshr_size(64 * NUM_CPUS)
.hit_latency(19)
.fill_latency(1)
.tag_bandwidth(NUM_CPUS)
.fill_bandwidth(NUM_CPUS)
.offset_bits(LOG2_BLOCK_SIZE)
.reset_prefetch_as_load()
.reset_virtual_prefetch()
.reset_wq_checks_full_addr()
.prefetch_activate(access_type::LOAD, access_type::PREFETCH)
.prefetcher<CACHE::pprefetcherDno>()
.replacement<CACHE::rreplacementDlru>()
CACHE::Builder::name
self_type & name(std::string name_)
Definition: cache.h:334

◆ default_ptw

const auto champsim::defaults::default_ptw
Initial value:
=
PageTableWalker::Builder{}.tag_bandwidth(2).fill_bandwidth(2).mshr_size(5).add_pscl(5, 1, 2).add_pscl(4, 1, 4).add_pscl(3, 2, 4).add_pscl(2, 4, 8)
PageTableWalker::Builder
Definition: ptw.h:90
PageTableWalker::Builder::mshr_size
Builder & mshr_size(uint32_t mshr_size_)
Definition: ptw.h:126
PageTableWalker::Builder::fill_bandwidth
Builder & fill_bandwidth(uint32_t max_fill_)
Definition: ptw.h:136
PageTableWalker::Builder::add_pscl
Builder & add_pscl(uint8_t lvl, uint32_t set, uint32_t way)
Definition: ptw.h:121
PageTableWalker::Builder::tag_bandwidth
Builder & tag_bandwidth(uint32_t max_read_)
Definition: ptw.h:131

◆ default_stlb

const auto champsim::defaults::default_stlb
Initial value:
= CACHE::Builder{}
.sets(128)
.ways(12)
.pq_size(0)
.mshr_size(16)
.hit_latency(7)
.fill_latency(1)
.tag_bandwidth(1)
.fill_bandwidth(1)
.offset_bits(LOG2_PAGE_SIZE)
.reset_prefetch_as_load()
.reset_virtual_prefetch()
.reset_wq_checks_full_addr()
.prefetch_activate(access_type::LOAD, access_type::PREFETCH)
.prefetcher<CACHE::pprefetcherDno>()
.replacement<CACHE::rreplacementDlru>()