Here is a list of all class members with links to the classes they belong to:

- r -

• ras : RAS< RAS_SIZE, CALL_INSTR_SIZE_TRACKERS >
• ras_index : RAS< RAS_SIZE, CALL_INSTR_SIZE_TRACKERS >
• read() : champsim::inf_istream< Tag, StreamType >
• read_and_update_sig() : spp::SIGNATURE_TABLE
• read_pattern() : spp::PATTERN_TABLE
• reader_model() : champsim::tracereader::reader_model< T >
• ready_packets : do_nothing_MRC , filter_MRC
• refresh_thresh : champsim::bulk_tracereader< T, F >
• reg_producers : O3_CPU
• region : my_predictor::regionentry
• regionentry() : my_predictor::regionentry
• registers_instrs_depend_on_me : ooo_model_instr
• reinit() : PREDICTOR
• release() : release_MRC
• release_all() : release_MRC
• release_MRC() : release_MRC
• remainder_tag : spp::PREFETCH_FILTER
• repeatable() : champsim::repeatable< T, Args >
• replacement() : CACHE::Builder< P_FLAG, R_FLAG >
• request_array_type : DRAM_CHANNEL
• request_type : CACHE , CacheBus , champsim::channel , DRAM_CHANNEL::request_type , MEMORY_CONTROLLER , PageTableWalker , queue_issue_MRP , to_pq_MRP , to_rq_MRP , to_wq_MRP
• reset_prefetch_as_load() : CACHE::Builder< P_FLAG, R_FLAG >
• reset_virtual_prefetch() : CACHE::Builder< P_FLAG, R_FLAG >
• reset_wq_checks_full_addr() : CACHE::Builder< P_FLAG, R_FLAG >
• response() : champsim::channel::response
• response_requested : champsim::channel::request
• response_type : CACHE , CacheBus , champsim::channel , DRAM_CHANNEL , MEMORY_CONTROLLER , PageTableWalker , queue_issue_MRP
• ret_addr : filter_MRC
• ret_data : do_nothing_MRC , release_MRC
• Retire_ch_i : my_predictor
• Retire_ch_t : my_predictor
• Retire_ptghist : my_predictor
• retire_rob() : O3_CPU
• retire_width() : O3_CPU::Builder< B_FLAG, T_FLAG >
• RETIRE_WIDTH : O3_CPU
• return_time : queue_issue_MRP::result_data
• returned : champsim::channel , counting_MRP , queue_issue_MRP
• ROB : O3_CPU
• rob_size() : O3_CPU::Builder< B_FLAG, T_FLAG >
• ROB_SIZE : O3_CPU
• roi_cache_stats : champsim::phase_stats
• roi_cpu_stats : champsim::phase_stats
• roi_cycle() : O3_CPU
• roi_dram_stats : champsim::phase_stats
• roi_instr() : O3_CPU
• roi_stats : CACHE , champsim::channel , DRAM_CHANNEL , O3_CPU
• row_buffer_hit : DRAM_CHANNEL::BANK_REQUEST
• RQ : champsim::channel , DRAM_CHANNEL
• RQ_ACCESS : champsim::cache_queue_stats
• RQ_FULL : champsim::cache_queue_stats
• RQ_MERGED : champsim::cache_queue_stats
• rq_occupancy() : champsim::channel
• RQ_ROW_BUFFER_HIT : dram_stats
• RQ_ROW_BUFFER_MISS : dram_stats
• RQ_SIZE : champsim::channel
• rq_size() : champsim::channel
• RQ_TO_CACHE : champsim::cache_queue_stats
• rtable : my_predictor