- d -

• data : CACHE::BLOCK , CACHE::mshr_type , CACHE::tag_lookup_type , champsim::channel::request , champsim::channel::response , champsim::msl::lru_table< T, SetProj, TagProj >::block_t , DRAM_CHANNEL::request_type , PageTableWalker::mshr_type
• dbus_count_congested : dram_stats
• dbus_cycle_available : DRAM_CHANNEL
• dbus_cycle_congested : dram_stats
• DECODE_BUFFER : O3_CPU
• DECODE_BUFFER_SIZE : O3_CPU
• DECODE_LATENCY : O3_CPU
• DECODE_WIDTH : O3_CPU
• decoded : ooo_model_instr
• delta : spp::GLOBAL_REGISTER , spp::PATTERN_TABLE
• destination_memory : cloudsuite_instr , input_instr , ooo_model_instr
• destination_registers : cloudsuite_instr , input_instr , ooo_model_instr
• DIB : O3_CPU
• dib_checked : ooo_model_instr
• dir : lentry
• direction_prediction_miss : cpu_stats
• dirty : CACHE::BLOCK
• DISPATCH_BUFFER : O3_CPU
• DISPATCH_BUFFER_SIZE : O3_CPU
• DISPATCH_LATENCY : O3_CPU
• DISPATCH_WIDTH : O3_CPU
• DRAM_DBUS_RETURN_TIME : MEMORY_CONTROLLER
• DRAM_DBUS_TURN_AROUND_TIME : MEMORY_CONTROLLER
• DRAM_WRITE_HIGH_WM : MEMORY_CONTROLLER
• DRAM_WRITE_LOW_WM : MEMORY_CONTROLLER